Electronic selection bingo game unit

ABSTRACT

The invention relates to a selection intersection selecting unit for a bingo game. There are 75 unique selection intersections in a bingo game, and this unit permits any one of the intersections to be selected with equal probability. The unit consists of an electronic circuit including a 5 X 15 switch matrix. The circuit further consists of a clock circuit means with a low frequency and a high frequency output, and a counter circuit driven by the output. The low frequency output is much greater than 75 c.p.s. The counter circuit drives the switch matrix, and the high frequency output is applied to the counter only during a low output of the matrix. The counter has two sets of outputs, one set containing 5 outputs and the other 15, and each set is connected to a different axis of the matrix. Thus, after each count, a different intersection of the matrix is selected and removed. The remaining intersections will then also be selectable with equal probability.

United States Patent 1 Friedman ELECTRONIC SELECTION BINGO GAME UNIT[76] lnventor: David Warren Friedman, No. 30-15,

2-chome Kakinokizaka, Meguro-ku. Tokyo. Japan [22] Filed: Aug. 9, I973[21] Appl. No.: 387,194

[30] Foreign Application Priority Data Jan. 23, 1973 Japan 48-9151 [52]US. Cl. 273/138 A; 340/323 [51] Int. Cl A631) 71/06; A63f 3/06 [58]Field of Search ..273/138 A, 1 E, 139,

130 AB, 273/134 A, 135 A, 135 B, 136 A; 340/323 [451 July 22,1975

Primary Examiner-Richard C. Pinkharn Assistant Examiner-Arnold W. KramerAttorney, Agent, or Firm-Wenderoth, Lind & Ponack [57] ABSTRACT Theinvention relates to a selection intersection selecting unit for a bingogame. There are 75 unique selection intersections in a bingo game, andthis unit permits any one of the intersections to be selected with equalprobability. The unit consists of an electronic circuit including a 5 X15 switch matrix. The circuit further consists of a clock circuit meanswith a low frequency and a high frequency output, and a counter circuitdriven by the output. The low frequency output is much greater than 75c.p.s. The counter circuit drives the switch matrix, and the highfrequency output is applied to the counter only during a low output ofthe matrix. The counter has two sets of outputs, one set containing 5outputs and the other 15, and each set is connected to a different axisof the matrix. Thus, after each count, a different intersection of thematrix is selected and removed. The remaining intersections will thenalso be selectable with equal probability.

6 Claims, 7 Drawing Figures SHEET PATENTEDJUL 22 ms m 5 nm n22PATENTEDJUL22|915 3.895807 SHEET 3 FIG.3

PATENTEDJUL 22 ms 3 8 95, 8 O7 sum 5 4 FIGS ELECTRONIC SELECTION BINGOGAME UNIT BACKGROUND OF THE INVENTION The present invention relates to abingo game unit making possible selection from among 75 unique selectionintersections with equal probability by utilizing electronic circuitmeans.

In units which have been in use heretofore for bingo, adjustment of theunit itself is difficult because of rocking, etc. when it is used onboard a boat, etc. Furthermore, such units have defects in that theballs used for selection have different weights, making it difficult toobtain a set of 75 balls yielding equal probability of selection.

The object of the present invention is to overcome the above-mentioneddefects and to provide a unit most appropriate for the bingo game whichis compact and requiring no adjustment, and is to obtain a bingo gameunit including an electronic clock circuit including a minimum timecontrol circuit capable of controlling the minimum operation time of aselection start switch and two clock circuits. A high frequency clockcircuit and a low frequency clock circuit are provided, both havingfrequencies sufficiently higher than 75 c.p.s.. A counter circuit isdriven by said electronic clock circuit and forms 75 unique selectionintersections, while a switch matrix circuit is driven by said countercircuit and has 75 intersection points equipped with 75electromechanical switches arranged in cartesian co-ordinate formcorresponding to selection intersections numbered from 1 through 75.Visual display units corresponding to said electromechanical switches ina one to one ratio are provided with a board consisting of the 75 visualdisplay units arranged in the system of cartesian coordinates equippedwith additional switches mechanically interlocked with saidelectromechanical switches, respectively, and having such acharacteristic which allows for removal of (75-M) selectionintersections already selected and memory of removed selectionintersections by means of the position of the abovementionedelectromechanical switches. A feedback circuit is driven by said switchmatrix circuit and provides a feedback control signal to the aforesaidelectronic clock circuit in order to select the output of the abovesaidlow frequency clock circuit as the output of the abovesaid electronicclock circuit and to allow selection of one of the selectionintersections when the feedback control signal is 1, and to select theoutput of the abovesaid high frequency clock circuit as the output ofthe abovesaid electronic clock circuit when the feedback control signalis 0, indicating memory of a previously removed selection intersection,arranged such that the probability of selecting any one selectionintersection from among M remaining selection intersections isessentially l/M. The selected intersection is indicated by means of theabovesaid visual display units and after operation of the switchassociated with the selected intersection of the switch matrix circuitthe visual indication is removed and the memory of the removed selectionintersection is displayed on the board of the visual display unitsmentioned above, and the system is further arranged such that the (75-M)selection intersections already removed may not be selected again.

DESCRIPTION OF THE DRAWINGS Preferred embodiments of the persentinvention will be described hereunder referring to the attached drawingsin which:

FIG. 1 is a perspective view which shows the external appearance of themain part H of bingo game unit embodying the principles of the presentinvention;

FIG. 2 is the main circuit diagram which shows an embodiment of the mainpart H;

FIG. 3 is a timing signal diagram of the outputs of each principalcircuit which occur in the case of per forming selection using the mainpart H;

FIG. 4a is a circuit diagram which shows the connection between thedisplaying board and electromechanical switches;

FIG. 4b is a perspective view of the displaying board;

FIG. 5 is an explanatory view which shows the audio unit connected tothe main part H;

FIG. 6 is a main circuit diagram including the audio circuit and theinitializing circuit.

DESCRIPTION OF THE EMBODIMENTS SHOWN HEREIN FIG. 1 shows the externalappearance of the main part H of the unit which is formed in almost theshape of a rectangular parallelepiped in which only the front surface 1is somewhat inclined from the bottom surface 2 towards the upper surface3. Located on the front surface 1 is the selection start switch 4 and apower supply switch 5. Located on the upper surface 3 are theintersection points I1 through I75 arranged in cartesian coordinate formconsisting of 5 columns and 15 rows where each of the five columnscorresponds to one of the five characters of the word BINGO, and eachintersection point contains an electromechanical switch, S1 through S75,and also a visual indicator unit 6 consisting of 5 lamps LXI through LXSforming a coordinate axis 7 and 15 lamps LYl through LY15, forming acoordinate axis 8. Thus, the visual indicator unit 6 indicatesintersection points with one to one correspondence. The visual indicatorunit 6 may have such a construction where one lamp is provided at eachand every intersection point, or light emitting diodes (LED) may be usedin place of lamps. When light emitting diodes are used at each and everyintersection point Il through I75, diodes D1 through D75 may be omitted.(See FIG. 2 and FIG. 6.)

FIG. 4b shows a visual display board 11. Board 11 is arranged in thesystem of cartesian coordinates and contains 75 numbered visual displayunits DSl through D875, and consists of a connector 13 containing 75actuating terminals and one common terminal in addition to a power cord14. Connector 13 is coupled with a mating connector 12 which isconnected to supplementary switches aSl through aS75 which aremechanically interlocked with electromechanical switches S1 through S75(See FIG. 4a).

The mating connector 12 and supplementary switches aSl through aS75 arecontained in the main part H of the unit. Accordingly, when a selectionintersection is selected, one of the electromechanical switches S1through S75 is switched OFF and the corresponding supplementary switchis switched ON, thus lighting the corresponding visual display unit. Itis unnecessary to point out that the switches S1 through S75 andsupplementary switches as] through aS75 may be so constructed so as toobtain interlocking movement so that the visual display units are turnedoff in the reverse manner. One lamp is used in the present embodimentfor each of the visual display units DSl through DS75 respectively.

On the front surface of board 11 the lamps are arranged behind acoloured glass surface. FIG. 2 shows the principal circuit of the mainpart H of the unit which is an embodiment of the present invention andis capable of selecting from among 75 unique selection intersections, inwhich E1 is the electronic clock circuit whose output is connected tothe counter circuit CO2 and further to the switch matrix circuit M3 andthe feedback circuit F4 successively, the feedback circuit F4 beingconnected back to the electronic clock circuit E1. The main circuit isactivated by an input control signal 15 from the selection start switch4 for the purpose of automatically selecting one of the selectionintersections, and the selection operation is made possible by means ofthe feedback control signal 16.

The object of the two clock circuits, A and B is to provide a unit timesignal for the electronic clock circuit E1 to drive the counter circuitCO2, and the low frequency clock circuit A consists of an astablemultivibrator circuit where the duty cycle and frequency F aredetermined at fixed values by selection of time constants t, and 2, Inthis embodiment, F is a square Wave at 1000 c.p.s. 1

The high frequency clock circuit B also consists of an astablemultivibrator similar to clock circuit A where duty cycle and frequencyF are determined at fixed values by selection of time constants t and 1Since the output Bo of clock circuit B is inhibited by a misselectionprevention circuit ERll during the time delay z,,=l/F,,, the frequency Pis obtained as F 2X(75+5)X10O0l6O,OOO c.p.s. Furthermore, bothfrequencies F and F are sufficiently larger than 75. In other words,even if any number of selection intersections or all 75 selectionintersections are removed, it is feasible to obtain a series ofnondeleted selection intersections during a single cycle having such acharacteristic that memory is accomplished by means of electromechanicalswitches S1 through S75 by setting the relationship between frequenciesF and F such that 80 cycles of the squarewave output of clock circuit Bfall within P (i.e. the negative pulse width of the squarewave output ofclock circuit A). (See FIG. 3). Connected to clock circuits A and B isselection circuit 9 which has the purpose of selecting between A or B0or neither by means of input control signal and the predeterminedfeedback control signal 16 and which consists of nand gates N15, N16 andN17.

When the output of the acquisition request memory circuit ME is O, theoutputs of nand gates N15 and N17 are inhibited. That is, the output ofnand gate N17 is 1 during this period. While the output of theacquisition request memory circuit ME is l and the output acrossresistor R21 is l, the output A0 of clock circuit A is selected as theinput of nand gate N15. Furthermore, when the output A0 is l, the outputof nand gate N15 is O, and when the output A0 is O, the output of nandgate N15 is 1. During this period, (when A0 o), the output of nand gateN16 is inhibited or 1.

During times when the output of the acquisition request memory circuitME is l and the output of resistor R21 is O and after an inhibit periodt l/F by means of the misselection prevention circuit ERll following thel to 0 transition of A0, the output B0 of clock circuit B is selected asthe output of nand gate N16. When the output B0 is 1, the output of nandgate N16 is 0, and when the output B0 is 0, the output of nand gate N16is 1. During this period, the output of nand gate N15 is 1. As describedabove, nand gate N17 responds only when the output of either nand gateN15 or N16 is 0. Furthermore, it is unnecessary to point out that theoutput of nand gate N17 is in phase withthe output A0 or B0 of eitherclock circuit A or B respectively. It should be noted that the outputsA0 and Bo have no particular phase relationship at any time. That is,outputs A0 and B0 are asynchronous.

The misselection prevention circuit ER11 consists o capacitor C3connected from the output A0 to one input of nand gate N16. Capacitor C3is discharged beginning when the output Ao makes a 1 to 0 transition andbefore the output of nand gate N16 could potentially make a l to 0transition. In other words, the object of this circuit is to prohibitselection of output B0 of clock circuit B as the output of nand gate N17during the delay time of approximately t =l/F A pulse forming circuit PS10 is connected to the output of nand gate N15 through capacitor C2coupled to the input of inverter 18, the output of which is connected tothe input of the acquisition circuit AQ7. When the output A0 of clockcircuit A makes a 0 to 1 transition, the output of nand gate N15 makes al to 0 transition which, coupled through capacitor C2, produces anegative pulse at the input of inverter 18. Thus, the output of inverter18 provides a positive pulse to the input of the acquisition circuit AQ7at the time immediately following a 0 to 1 transition of A0.

The acquisition circuit AQ7 consists of nand gate N19, having threeterminals on the input side and one terminal on the output side. Afterthe selection start switch 4 is operated and released, the output ofinverter 5a of the minimum time control circuit MNS makes a 0 to 1transition. When and if a selection intersection is selected at the sametime or with a slight delay with respect to the 0 to 1 transition ofinverter 5a, the output Ao will make a 0 to 1 transition and the outputof the pulse forming circuit PS10 will be a positive pulse and at thistime the output of the acquisition circuit AQ7 makes a l to 0 transitionwhich resets the acquisition request memory circuit ME. In other words,the operation of this circuit AQ7 is that of a monitor circuit whosepurpose is to suspend the output 13 of the abovementioned selectioncircuit 9 (i.e. the output of the electronic clock circuit E1) byresetting the said acquisition request memory circuit ME and therebysuspending further operation of the counter circuit CO2 when all theoutputs of the inverter 5a, the resistor R21 and the pulse formingcircuit P810 are l.

The minimum time control circuit MNS consists of a monostablemultivibrator circuit comprising nand gate N5b, inverter 5a andcapacitor C1. The said monostable multivibrator circuit is in a stablecondition when the selection start switch 4 is in an ON or 0 conditionor ordinary OFF or 1 condition, but a pulse having a fixed pulse widthis generated as the output of said minimum time control circuit MNSduring the time capacitor c1 is'discharging. This prevents the possiblerapid operation of selection start switch 4 from generating a very shortpulse at the output of inverter 5a such that it is almost predictablethat selection of closely following selection intersections would occur.

In other words, the minimum operation time of selection start switch 4can be controlled. Thus, it becomes feasible to always acquire theaforementioned selection intersection with essentially equal probabilitywithout any effect caused by the operating time of the selection startswitch 4. The inhibit circuit ll-I6 is provided for the purpose ofpreventing a further selection until the correct switch located at theintersection point in the switch matrix circuit M3 is operated (i.e.open contacts) corresponding to the selection intersection to beremoved. The circuit consists of nand gate N6b and inverter 6a.

When the selection start switch 4 is ON or O in the process ofselecting, the output of nand gate N5b in the minimum time controlcircuit MN5 is 1. Even if an operator who performs selection does notoperate (i.e. open contacts) the switch, corresponding to the alreadyselected selection intersection, by mistake and desires to performselection, the lamps remain lit and the output of inverter 6a is 0 sincethe output of resistor R21 (i.e. the feedback control signal 16) is 1,thus inhibiting the output of nand gate N6b (i.e. the output is held at1). When the operator operates the switch corresponding to the alreadyselected selection intersection, the feedback control signal 16 becomes0 and the output of inverter 6a becomes 1. Accordingly, the output ofnand gate N6b becomes 0 corresponding to the feedback control signal 16during a time when the selection start switch 4 is ON or 0.

The acquisition request memory circuit ME has the purpose of providing aresettable memory of one bit until the said acquisition request memorycircuit ME is set for the purpose of allowing operation of clockselection circuit 9, and comprises a set/reset FLIP-FLOP consisting ofnand gates N8a and N8b. It is set such that the output of nand gate N8abecomes a I when the output of nand gate N6b is momentarily O and isreset so as to obtain a 0 output from nand gate N8a when the output ofthe acquisition circuit AQ7 is momentarily 0.

FIG. 2 shows the details of the counter circuit C02. The counter circuitCO2 is driven by the electronic clock circuit E1, and consists ofcounter circuits X and Y constructed by using binary counter stages anddecoders DX and DY, and is operated by the output 13 of the aforesaidelectronic clock circuit E1. In FIG. 2, the counter circuit X consistsof a three stage sequential type binary counter stages B1, B2 and B3,and the outputs of stages B1 and B3 are connected to the inputs of nandgate N20, the output of which is feedback to reset terminals BRl, BR2and BR3 of binary counter stages B1, B2 and B3 respectively. Thus ascale-of-5 counter circuit is formed. In other words, five differentoutput combinations are possible so as to correspond to a series ofunique selections which are mutually exclusive. The logical value ofnand gate N20 is Q1.Q3, and the binary counter stages B1, B2 and B3 arereset at that time only. Here, Q1 and Q3 are the output logical valuesof the respective binary counter stages B1 and B3.

The nand gates N21 through N25 constitute a decoder DX and usually havean output of l, but the output being selected at any moment has anoutput of 0. In FIG. 2, a counter circuit Y consists of four stages ofbinary counters connected in series B4 through B7, and 16 (i.e. 2")output combinations are possible so as to correspond to a series ofunique selections which are mutually exclusive, but one combination isnot used.

Counter circuit Y is connected to the 4 input terminals of each of nandgates N26 through N41, each gate having one output terminal. Nand gateN26 is not used, as mentioned above. The output condition of countercircuit Y is similar to the output condition of counter circuit Xpreviously mentioned.

Since the counter circuits X and Y divide the squarewave of theelectronic clock selection circuit El by 5 and 16 respectively, and aclock pulse is generated by means of a nand gate, they generate onedecoder pulse each in such a way that the output pulses of decoders DXand DY are invariably in phase with each other at any time.

The purpose of switch matrix circuit M3 is to provide memory forselection intersections already removed through selection, and consistsof driving transistors TR1 through TRS and TR6 through TR20, resistorsR1 through R5 and R6 through R20, diodes D1 through D75 and 75 switchesS1 through S75, being driven by the aforementioned counter circuit CO2where selection intersections are arranged by using one decoder pulseeach from decoder DX and decoder DY corresponding tb the above-mentionednumbered intersections. Here, since nand gate N26 is not used asdescribed above, 1 X 5 5 intersections are not formed as selectionintersections, but the feedback control signal 16 is O at such times andthis causes output B0 to be selected as the output of the electronicclock circuit E1. Thus, 75 selection intersections are produced and arearranged at each point of intersection of the switch matrix circuit M3.Simultaneously, the switch matrix circuit M3 displays which selectionintersection is selected by means of a visible display 6 using lamps. Alight emitting diode may be substituted for each lamp as well. Also, theswitch matrix circuit M3 displays whether previously selected selectionintersections have been removed or not by means of the position (i.e. ONor OFF) of each switch in the matrix.

In selection generated by means of coincidence of one decoder pulse fromdecoder DX at an arbitrary time together with a decoder pulse fromdecoder DY corresponding to the aforesaid clock pulse, for example, inthe case of nand gate N21 and nand gate N40, the current from the powersupply B+ flows through lamp LXI, driving transistor TRl, switch S1,diode D1, driving transistor TR19 and lamp LY2 to resistor R21. Thus, apotential difference is produced across resistor R21 and the feedbackcontrol signal 16 having a 1 output is feedback to the aforesaidelectronic clock circuit El, because one end of resistor R21 isconnected to ground. Diodes D1 through D75 are provided for the purposeof preventing the current from flowing through lamps other than theselected set.

Feedback circuit F4 consists of resistor R21 driven by theabove-mentioned switch matrix circuit M3 and is capable of transferringthe memory of removed selection intersections to the electronic clockcircuit E1 by means of the feedback control signal 16 such thatselection may be feasible only when the output of said resistor R21 is land the output of clock circuit A is in a predetermined output conditionhaving just made a 0 to 1 transition. A detailed description of the modeof selection during a same using the Bingo Game unit of the presentinvention will be made hereafter. Initially, all switches S1 through S75of the switch matrix circuit M3 are ON (i.e. closed contacts), theselection start switch 4 is OFF, the feedback control signal 16 is l andthe output of the acquisition request memory circuit ME is 0. Thus, nandgate N17 is inhibited and the output 15 of the electronic clock circuitE1 has a 1 output having no relationship to outpus A and B0 of clockcircuits A and B respectively. The current flowing through the selectedselection intersection switch is then interrupted by operation of theappropriate switch (i.e. one of S1 through S75) in the switch matrixcircuit M3 causing the feedback control signal 16 to become 0 whichcauses the output of inverter 6a to become 1 which enables nand gateN6b. Next, when selection start switch 4 is operated ON in order tobegin selection of any one of a series of selection intersections of asingle cycle consisting of M selection intersections, the acquisitionrequest memory circuit ME is set which causes its output to change fromO to l and the aforesaid nand gate N17 is enabled. Furthermore, sincenand gate N is inhibited, selection of squarewave F becomes impossibleand such a condition allowing selection of squarewave F is obtained.

Squarewave F advances the counter circuit CO2 to the point where thenext selection intersection not previously removed allows current toflow through resistor R21 causing the feedback control signal 16 tobecome 1 and thus inhibit nand gate N16 and enable nand gate N15 therebyselecting squarewave F A as the output 13 of nand gate N17 which is O atthat time until the end of negative pulse P. This process is repeatedmany times while selection start switch 4 is held ON. Also, at the endof every negative pulse P when squarewave F and the output 13 of nandgate N17 make a O to 1 transition, the output of nand gate N15 makes a lto 0 transition which is coupled to inverter 18 through C2 causing apositive pulse to appear at the output of inverter 18.

Next, depending on the operator, selection start switch 4 is released orplaced OFF enabling one input of acquisition circuit AQ7. When by meansof either F or F selection, the counter is advanced to a selectionintersection not yet deleted causing feedback control signal 16 tobecome 1, another input of acquisition circuit AQ7 is enabled. Finally,at the end of negative pulse P, the output of inverter 18 provides aposi tive pulse fully enabling acquisition circuit AQ7 such that duringthe pulse time, the output of nand gate N19 becomes 0 resetting theacquisition request memory circuit ME output to O and in turn inhibitingthe clock output 13 of clock selection circuit E1 thus completing thesingle selection cycle wherein a single selection intersection isselected. In other words, a series of selection intersections of asingle cycle consisting of M cycles of squarewave A0 of clock circuit Ais arranged in such a way that one of M unique selection intersectionsand the transition from 0 to 1 of A0 correspond to each other in everycycle.

Furthermore, since F 1000 c.p.s. and is sufficiently large compared toN==75 and also due to the operation of minimum time control circuit MNS,the probability of selecting any one of 75 selection intersections issubstantially 1/75, which is equal to the probability of selecting anyother one of the 75 selecrent from the power supply B+ does not flowthrough the intersection point corresponding to the aforesaid selectionintersection which has already been removed and the output acrossresistor R21 (i.e. the feedback control signal 16) is 0. Accordingly,the 1 input of nand gate N15 is changed to O and the 0 input of nandgate N16 is changed to 1, thus output A0 is inhibited and output B0 isselected as output 13 of the above mentioned electronic clock circuitE1.

Also, since the frequency of clock circuit B is F l60,000 c.p.s., 80cycles of B0 can be contained within the negative pulse portion P of theaforementioned clock circuit A and the 0 to 1 change of the output A0 isstill obtained even if any number of totally :i selection intersectionshave been removed, and it is feasible to select selection intersectionsin any case. In other words, the switch matrix circuit M3 has such acharacteristic that any number or the total number of selectionintersections can be removed and memorized by means of the switches.Furthermore, the circuit is arranged such that selection is performedindependently of the (75-M) selection intersections already removed andthe probability of selecting any one selection intersection is l/M whichis equal to the probability of selecting any other one, and further, sothat the (75-M) selection intersections already removed are preventedfrom being selected again by means of the feedback control signal 16.The mode of selection during a game using the Bingo Game Unit of thepresent invention has been fully described above. However, as shown inFIG. 5 and FIG. 6, as a second embodiment, mechanical sound may beprojected to the players to enhance enjoyment of players through aspeaker 21 driven by audio unit 20 which has as its inputs the usualmicrophone 22 where person 23 reads the number of the selected selectionintersection and also an input from audio circuit AU contained in themain unit H.

Audio circuit AU consists of nand gate N42, capacitors C4 and C5 and asound output connector 24. Output A0 of clock circuit A is one input ofnand gate N42 and output Q7 of binary counter stage B7 is coupledthrough capacitor C4 to a second input while the remaining third inputis the feedback control signal 16. The output of nand gate N42 iscoupled to sound output connector 24 through capacitor C5. Further, in athird embodiment, an initializing circuit IC is incorporated. Thecircuit consists of nand gate N43, capacitor C6 and resistor R22 and theoutput of nand gate N43 is connected to reset terminals BR4 through 8R7of binary counter stages B4 through B7 respectively. One input of nandgate N43 is the output of nand gate 3b of acquisition request memorycircuit ME while the other is from the power supply B through capacitorC6. This initializing circuit IC changes the mode of selection slightlyonly at the beginning where upon application of power supply B+ none ofthe N=75 selection intersections are selected to begin with.

Thus, it is feasible, using the Bingo Game Unit of the presentinvention, to perform successive selection with equal probability fromamong 75 uniquely numbered selection intersections or fewer dependingupon how many have already been removed. Futhermore, no adjustments arerequired, operation of the unit is almost automatic and it is easy tosee which selection intersections have already been removed.

I claim:

1. An equal probability selection electronic device a switch matrixcomprised of 75 slide switches arranged in a X 15 Cartesian coordinateform, each slide switch being used to indicate a selection intersectionand being individually controllable by the operation of the humanoperator to define whether 10 or not the slide switch is selectable andlamp indicators operatively positioned to define the intersectionselected at the time of selection;

a selector circuit coupled to said switch matrix and comprised ofcounter circuit means for successively addressing the slide switches;

clock circuit means coupled to said counter circuit means for drivingthe counter circuit means and providing a clock pulse output having oneof a relatively high and relatively low frequency, the relatively highfrequency being used only to sweep past any addresses previouslyselected;

feedback circuit means connected between the switch matrix and the clockcircuit means for controlling said clock pulse output such that theclock pulse output is selected to be of low frequency when a selectableslide switch is being addressed and is otherwise selected to be of highfrequency; and

selection start switch means arranged to provide, by successive operatoruse for each desired selection, both a start signal to the clock circuitmeans for initiating a selection of a slide switch and a stop signal forinitiating termination of a selection cycle, the arrangement being suchthat the clock pulse output may be stopped only when a selectable slideswitch is addressed, which occurs at equal time segments of theaddressing sequence, regardless of the number of slide switches nolonger selectable.

2. A device as recited in claim 1 wherein said clock 3. A device asrecited in claim 1, wherein said clock circuit means comprises a highfrequency clock to provide said high frequency output, and a lowfrequency clock to provide said low frequency output, the low frequencyin Hertz being numerically much greater than the number of slideswitches, and the high frequency in Hertz being numerically greater than(2N) (low frequency output), where N is equal to 5 X 16 80.

4. A device as recited in claim 3 wherein said clock circuit means hasclock frequencies which are asynchronous and further comprising amisselection prevention circuit means operatively coupled and driven bythe low frequency clock to inhibit the high frequency clock for a delaytime of l/(the high frequency output), which eliminates erroneousadvancement of the counter circuit means due to the arbitrary phaserelationship of the high frequency asynchronous clock with respect tothe low frequency asynchronous clock.

5. A device as recited in claim 3 further comprising an acquisitionrequest memory operatively coupled to said clock circuit means, aminimum time control circuit means for controlling the minimum operationtime of a selection start switch, and inhibit circuit means, saidinhibit circuit means including a nand gate for preventing operation ofthe acquisition request memory until after a currently selectedselection intersection has been removed by opening the contacts of theslide switch corresponding to the currently selected selectionintersection, one input of said nand gate being connected through aninverter to the feedback circuit means and another input thereof beingdirectly connected to the output of said minimum time control circuitmeans, the output of said nand gate being connected to said acquisitionrequest memory, said inhibit circuit means being enabled by a change inthe signal from said feedback circuit means when the slide switchcorresponding to the selected selection intersection is opened, andthereby causing deletion of that selection intersection from futureconsideration.

6. A device as recited in claim 1 further comprising an acquisitionrequest memory operatively coupled to said clock circuit means, aminimum time control circuit means for controlling the minimum operationtime of a selection start switch, and inhibit circuit means, saidinhibit circuit means including a nand gate for preventing operation ofthe acquisition request memory until after a currently selectedselection intersection has been removed by opening the contacts of theslide switch corresponding to the currently selected selectionintersection, one input of said nand gate being connected through aninverter to the feedback circuit means and another input thereof beingdirectly connected to the output of said minimum time control circuitmeans, the output of said nand gate being connected to said acquisitionrequest memory, said inhibit circuit means being enabled by a change inthe signal from said feedback circuit means when the slide switchcorresponding to the selected selection intersection is opened andthereby causing deletion of that selection intersection from futureconsideration.

1. An equal probability selection electronic device for a bingo gameallowing a human operator to make, by successive operation, theselection of any one of 75 (or fewer, if some are not selectable) uniqueselection intersections, comprising: a switch matrix comprised of 75slide switches arranged in a 5 X 15 Cartesian coordinate form, eachslide switch being used to indicate a selection intersection and beingindividually controllable by the operation of the human operator todefine whether or not the slide switch is selectable and lamp indicatorsoperatively positioned to define the intersection selected at the timeof selection; a selector circuit coupled to said switch matrix andcomprised of counter circuit means for successively addressing the slideswitches; clock circuit means coupled to said counter circuit means fordriving the counter circuit means and providing a clock pulse outputhaving one of a relatively high and relatively low frequency, therelatively high frequency being used only to sweep past any addressespreviously selected; feedback circuit means connected between the switchmatrix and the clock circuit means for controlling said clock pulseoutput such that the clock pulse output is selected to be of lowfrequency when a selectable slide switch is being addressed and isotherwise selected to be of high frequency; and selection start switchmeans arranged to provide, by successive operator use for each desiredselection, both a start signal to the clock circuit means for initiatinga selection of a slide switch and a stop signal for initiatingtermination of a selection cycle, the arrangement being such that theclock pulse output may be stopped only when a selectable slide switch isaddressed, which occurs at equal time segments of the addressingsequence, regardless of the number of slide switches no longerselectable.
 2. A device as recited in claim 1 wherein said clock circuitmeans has clock frequencies which are asynchronous and furthercomprising a misselection prevention circuit means operatively coupledand driven by said clock circuit means with a low frequency to inhibit ahigh frequency for a delay time of 1/(the high frequency output), whicheliminates erroneous advancement of the counter circuit means due to thearbitrary phase relationship of the high frequency with respect to thelow frequency.
 3. A device as recited in claim 1, wherein said clockcircuit means comprises a high frequency clock to provide said highfrequency output, and a low frequency clock to provide said lowfrequency output, the low frequency in Hertz being numerically muchgreater than the number of slide switches, and the high frequency inHertz being numerically greater than (2N'') . (low frequency output),where N'' is equal to 5 X 16
 80. 4. A device as recited in claim 3wherein said clock circuit means has clock frequencies which areasynchronous and further comprising a misselection prevention circuitmeans operatively coupled and driven by the low frequency clock toinhibit the high frequency clock for a delay time of 1/(the highfrequency output), which eliminates erroneous advancement of the countercircuit means due to the arbitrary phase relationship of the highfrequency asynchronous clock with respect to the low frequencyasynchronous clock.
 5. A device as recited in claim 3 further comprisingan acquisition request memory operatively coupled to said clock circuitmeans, a minimum time control circuit means for controlling the minimumoperation time of a selection start switch, and inhibit circuit means,said inhibit circuit means including a nand gate for preventingoperation of the acquisition request memory until after a currentlyselected selection intersection has been removed by opening the contactsof the slide switch corresponding to the currently selected selectionintersection, one input of said nand gate being connected through aninverter to the feedback circuit means and another input thereof beingdirectly connected to the output of said minimum time control circuitmeans, the output of said nand gate being connected to said acquisitionrequest memory, said inhibit circuit means being enabled by a change inthe signal from said feedback circuit means when the slide switchcorresponding to the selected selection intersection is opened, andthereby causing deletion of that selection intersection from futureconsideration.
 6. A device as recited in claim 1 further comprising anacquisition request memory operatively coupled to said clock circuitmeans, a minimum time control circuit means for controlling the minimumoperation time of a selection start switch, and inhibit circuit means,said inhibit circuit means including a nand gate for preventingoperation of the acquisition request memory until after a currentlyselected selection intersection has been removed by opening the contactsof the slide switch corresponding to the currently selected selectionintersection, one input of said nand gate being connected through aninverter to the feedback circuit means and anOther input thereof beingdirectly connected to the output of said minimum time control circuitmeans, the output of said nand gate being connected to said acquisitionrequest memory, said inhibit circuit means being enabled by a change inthe signal from said feedback circuit means when the slide switchcorresponding to the selected selection intersection is opened andthereby causing deletion of that selection intersection from futureconsideration.